Porous Silicon Fabrication
Development of the Technology for Fabrication of Porous Silicon on Insulating Substrate Applicable for Uncooled Microbolometer IR Photodetectors
Tech Area / Field
- MAT-ELE/Organic and Electronics Materials/Materials
- INS-DET/Detection Devices/Instrumentation
8 Project completed
Senior Project Manager
Bunyatov K S
State Institute of Rare Metals, Russia, Moscow
- NPO Orion, Russia, Moscow
- New Jersey Institute of Technology, USA, Newark\nDe Montfort University, UK, Leicester
Project summaryPorous silicon (PS) is an excellent material for its use as a sacrificial layer (SL) in fabrication process of membranes, bridges, cantilevers and other complicated constructions  needed for different devices, such as gaseous sensors, pressure detectors, capacitive microphones, thermopiles, etc. One of the most significant advantages of this material is enormous area of its pores that provides high rate of etching PS SL off at room temperature. Crystalline silicon (c-Si) and silicon oxide were mainly used earlier as SL. But a very long time is required for lateral (tens of micrometers) etching them off the lying above membrane or the bridge leading to destruction of these constructions. Prolonged chemical treatment also has a negative effect on other elements of microchip. PS is also a perfect sacrificial layer from the viewpoint of lithography because its smooth surface is suitable for deposition of thin layers. PS technology is completely compatible with standard silicon microchips manufacturing technology.
Traditional technology of PS layer fabrication based on anodization process of c-Si using direct current provides a possibility to obtain PS layers of different thickness and porosity. However, there are some applications where SL would cover insulating layer or electronic driving elements (like transistors) having high resistance with respect to direct current. Traditional process of PS SL formation is impossible in this case, and possible alternative is proposed in this project. The aim of this project is to develop the technology of formation PS layer on insulating substrate using alternating current and removal of PS layer using dry etching.
The possibility of electrochemical AC etching of c-Si, poly-Si and a-Si will be studied together with the properties of resulting PS layers. Profits of this technology will be demonstrated by applying it for fabrication of microbolometers with the design analogous to that of Raytheon System Company and Lockheed Martin [2,3]. However, this technology can also be used for fabrication of other micro-machined devices, for example sensors.
Microbolometer array - based photodetector devices (PD) are used in night vision, surveillance safeguard systems, missile tracking, temperature profiling in manufacturing, early fire detection, distant survey of electronic devices, etc. Microbolometer array contains 50ґ50 mm sized bolometer elements. Bridge – type element consists of vanadium oxide layer (thermal sensitive resistor) suspended above the substrate including driving transistor [2,3] and insulating layers. Vacuum gap between the suspended plate and the substrate provides thermal insulation. Layers of the bridge are initially deposited on the sacrificial layer, which is etched off at the final stage of structure fabrication. SL is ordinary a polyimide layer, but because the polyimide is not stable at above 450°C, VOx layer is made using vanadium deposition in oxygen atmosphere at temperatures close to 450 °C. Such a way formed VOx layers have temperature coefficient of resistance (TCR) of -(2-2.5)%/K. However, it is known that annealing of VOx layer in oxygen atmosphere at 500-600 °C transforms it to vanadium dioxide VO2 having significantly higher TCR of –5%/K approximately .
In this project it is supposed to use porous silicon as a sacrificial layer. This material is thermally stable at high temperatures and its use allows to perform annealing of VOx thus enhancing sensitivity of microbolometers. Highly sensitive microbolometers of two designs will be fabricated during this project. First design is above described bridge construction with PS sacrificial layer (made from poly-silicon or amorphous silicon layer). Second design is a membrane construction with PS SL made from the top layer of driving transistor followed by dry etching of PS. Resulting construction will be arranged in the plane of the substrate, which could increase its mechanical stability.
Several difficulties will be encountered during this project.
First of all, AC electrochemical etching was not earlier used for fabrication of PS, especially for fabrication of PS on insulating layer. Using c-Si substrates without an insulating layer, we have successfully performed several processes of AC PS fabrication. AC formation of PS from c-Si substrates was then made with series connected condenser which significantly obstructs the AC etching process. We have performed preliminary analysis of AC etching process and found technological conditions leading to experimentally confirmed AC formation of PS through a condenser. But a large scope of technological elaborations is still required in order to fabricate PS layers with desired parameters using AC etching.
Second, besides the necessity of detailed study of AC etching c-Si substrates, an AC etching of poly-Si and amorphous Si (a-Si) would also be studied.
PS layers formed from poly-Si and a-Si materials were not earlier used as sacrificial layers. The process of PS formation from poly-Si and a-Si using traditional DC electrochemical etching is studied too much lower extent as compared to that of PS formation from c-Si. Up to now more than 0.5 mm thick PS layers was not made from poly-Si and a-Si. The possibility to use light assistance in the process of PS formation will be considered.
The effect of thermal oxidation on the properties of PS will be studied. Because PS silicon crystallites are of several nanometers size, PS is rapidly thermally oxidized (completely oxidized during several minutes at 950 °C). Oxidized PS has a high mechanical stability and does not destroy at temperatures below 1,000 °C. The rate of chemical removal (etching off) is also very high for oxidized PS. Ordinarily PS SL is removed in KOH solution, but the etching in this electrolyte results in the destruction of the bridge suspended above thin (micrometer sized) air gap . The destruction occurs due to the condensation of water being present in etching solution. We will therefore try to perform the dry etching of PS.
As a result of project completion it will be first time developed a technology for fabrication of porous silicon layers from crystalline- polycrystalline- and (or) amorphous- silicon using alternating current electrochemical etching. There will be studied electrical, photoelectric and optical properties of AC fabricated PS, as well as the quality of its surface. Proposed fabrication method is the only possible one provided that PS layer is to be fabricated on insulating layers or on the crystalline substrate with electronic components (for example, transistors) inside it. In these cases a traditional direct current electrochemical etching method is non-applicable because insulators do not allow DC to flow.
Developed technology could be applied for example for preparation of PS – based sacrificial layers which are used in fabrication process of different bridge – type sensors: gas sensors, pressure sensors, microphones, thermopiles, microbolometers and the arrays of these devices. Proposed technology would allow for preparation of PS sacrificial layers with following parameters: thickness up to 2 mm (1m for membrane - type micro-machined elements), surface roughness below 0.05 mm, mechanical stability with respect to thermal treatment – at least 2 hours at 750 °C, time of complete removal from the air gap of 2 mm thickness and 50ґ50 mm area – no more than 3 minutes at room temperature (longitudinal etching rate 8.5 mm/min). Benefits of proposed technology will be demonstrated by fabrication of microbolometers and of linear bolometric array with at least 32 elements. It is supposed that the use of PS SL will give rise to the increase of temperature coefficient of resistance of vanadium oxide from 2%/K to 5%/K with corresponding increase of sensitivity of the bolometers and bolometric PD and an enhancement of the major parameter of uncooled bolometric thermographers (noise equivalent temperature difference - NETD) 2-2.5 times.
Project participants have necessary equipment and significant experience in design and fabrication of photodetector devices (including microbolometers - based PD) and microchips using MOS and CMOS technologies [5,6]. We fabricated 64ґ64 plane arrays of microbolometers and tested them by visualisation of static and dynamic thermal images. There is also a significant experience in fabrication and investigation of PS layers and PS - based device structures. In particular, we fabricated PS – based photodetectrors with higher photosensitivity in ultraviolet range of spectrum and close noise and response time as compared to c-Si based photodiodes [7,8]. Transport properties of oxidized and non-oxidized PS – based structures were investigated [9-13]. There were also studied optical properties and photoluminescence of oxidized and non-oxidized PS [14-16].
Foreign collaborators will determine the possible direction of the project activities, participate in the analysis of obtained scientific results and join publications. There will be performed crosschecks of results obtained in the course of the project implementation. This project will provide its participants (weapon scientists) with a opportunity to redirect their activity to civil need elaborations. The project will assist Russian scientists to integrate into international scientific community, and to perform joint investigations in science – capacious area of modern opto-electronics.
Projects’ activities follow:
1. Electrochemical AC fabrication of PS layers from c-Si, poly-Si and a-Si layers deposited on c-Si substrate and study of PS layers.
2. Electrochemical AC fabrication of PS layers from poly-Si layers deposited on dielectric layer (silicon nitride or silicon oxide) and study of PS layers. Study the possibility of fabrication thick (>1 mm) PPS layers by chemical etching.
3. Electrochemical AC fabrication of PS layers from a-Si layers deposited on dielectric layer.
4. Working out of photolithography process on poly-Si, a-Si, and PS.
5. Electrochemical AC fabrication of PS layers from top part of driving transistor and study of PS layers.
6. Electrochemical AC fabrication of PS islands from local (micrometre sized) areas of poly-Si and a-Si deposited on dielectric layers and (or) transistors.
7. Fabrication of bridge – type and (or) membrane – type microbolometers and microbolometric linear arays using PS SL.
The attempts will be made to perform the electrochemical etching process of c-Si, poly-Si and a-Si at different AC frequencies and amplitudes, different electrolyte composition, and with illumination assistance. The process will be studied by in-situ measurements of current-voltage dependencies and impedance of electrochemical cell.
Following properties of obtained PS layers will be studied: composition (by IR spectroscopy), impedance of metal/PS/c-Si structures, photoluminescence, optical absorption in visible region, surface homogeneity and roughness by optical microscopy and scanning electron microscopy.
The technology of microbolometric array fabrication using PS SL will be developed. Electrical and thermal properties of obtained microbolometers will be studied.
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